library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity	tx_mux is
	port( clk_100m:	     in std_logic;
		  da:            in std_logic_vector(7 downto 0);
		  clk_12m,sel:   out std_logic;		   
	      dout:          out std_logic_vector(7 downto 0);
	      led:           out std_logic_vector(1 downto 0)	     
		);
end entity;
architecture be of tx_mux is
signal cn:	           std_logic_vector(7 downto 0);
signal daa:	           std_logic_vector(7 downto 0);
begin
   	clk_12m<=cn(2);
	sel<=not cn(2);
	process(clk_100m)
	begin
		if clk_100m'event and clk_100m='1' then
		   cn<=cn+1;
		   if conv_integer(cn(1 downto 0))=1 then
		      daa<=da;   dout<=daa;		   	
		   end if;
		--   if conv_integer(cn(1 downto 0))=1 then
		--      dout<=daa;		   	
		--   end if;
	    end if;		
	end process;
	process(clk_100m)
	begin
		if clk_100m'event and clk_100m='1' then
		   if conv_integer(cn(2 downto 0))=2 then
		      led(0)<=not daa(2);		      
		   elsif conv_integer(cn(2 downto 0))=6 then
		      led(1)<=not daa(2);		     	     
		   end if;
		end if;
	end process;		
end be;
